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Error messages are all either prefixed with the name of the program (usually `make'), or, if the error is found in a makefile, the name of the file and linenumber containing the problem.
In the table below, these common prefixes are left off.
make
errors at all. They mean that a
program that make
invoked as part of a command script returned a
non-0 error code (`Error NN'), which make
interprets
as failure, or it exited in some other abnormal fashion (with a
signal of some type).
If no ***
is attached to the message, then the subprocess failed
but the rule in the makefile was prefixed with the -
special
character, so make
ignored the error.
make
's generic "Huh?" error message. It means that
make
was completely unsuccessful at parsing this line of your
makefile. It basically means "syntax error".
One of the most common reasons for this message is that you (or perhaps
your oh-so-helpful editor, as is the case with many MS-Windows editors)
have attempted to indent your command scripts with spaces instead of a
TAB character. Remember that every line in the command script must
begin with a TAB character. Eight spaces do not count.
make
command (such as a variable assignment). Command scripts
must always be associated with a target.
The second form is generated if the line has a semicolon as the first
non-whitespace character; make
interprets this to mean you left
out the "target: dependency" section of a rule.
make
decided it needed to build a target, but
then couldn't find any instructions in the makefile on how to do that,
either explicit or implicit (including in the default rules database).
If you want that file to be built, you will need to add a rule to your
makefile describing how that target can be built. Other possible
sources of this problem are typos in the makefile (if that filename is
wrong) or a corrupted source tree (if that file is not supposed to be
built, but rather only a dependency).
make
couldn't find any makefiles to read in.
The latter means that some makefile was found, but it didn't contain any
default target and none was given on the command line. GNU make
has nothing to do in these situations.
make
allows commands to be specified only once per target
(except for double-colon rules). If you give commands for a target
which already has been defined to have commands, this warning is issued
and the second set of commands will overwrite the first set.
make
detected a loop in the dependency graph:
after tracing the dependency yyy of target xxx, and its
dependencies, etc., one of them depended on xxx again.
make
variable
xxx that, when its expanded, will refer to itself (xxx).
This is not allowed; either use simply-expanded variables (:=
) or
use the append operator (+=
).
%
).
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