The machine instruction sets are (almost by definition) different on
each machine where as runs. Floating point representations
vary as well, and as often supports a few additional
directives or command-line options for compatibility with other
assemblers on a particular platform. Finally, some versions of
as support special pseudo-instructions for branch
optimization.
This chapter discusses most of these differences, though it does not include details on any machine's instruction set. For details on that subject, see the hardware manufacturer's manual.
as has no additional command-line options for the AMD
29K family.
The macro syntax used on the AMD 29K is like that described in the AMD
29K Family Macro Assembler Specification. Normal as
macros should still work.
`;' is the line comment character.
The character `?' is permitted in identifiers (but may not begin an identifier).
General-purpose registers are represented by predefined symbols of the
form `GRnnn' (for global registers) or `LRnnn'
(for local registers), where nnn represents a number between
0 and 127, written with no leading zeros. The leading
letters may be in either upper or lower case; for example, `gr13'
and `LR7' are both valid register names.
You may also refer to general-purpose registers by specifying the register number as the result of an expression (prefixed with `%%' to flag the expression as a register number):
%%expression
---where expression must be an absolute expression evaluating to a
number between 0 and 255. The range [0, 127] refers to
global registers, and the range [128, 255] to local registers.
In addition, as understands the following protected
special-purpose register names for the AMD 29K family:
vab chd pc0 ops chc pc1 cps rbp pc2 cfg tmc mmu cha tmr lru
These unprotected special-purpose register names are also recognized:
ipc alu fpe ipa bp inte ipb fc fps q cr exop
The AMD 29K family uses IEEE floating-point numbers.
.block size , fill
.cputype
.file
Warning: in other versions of the GNU assembler,
.fileis used for the directive called.app-filein the AMD 29K support.
.line
.sect
.use section name
.text, .data,
.data1, or .lit. With one of the first three section
name options, `.use' is equivalent to the machine directive
section name; the remaining case, `.use .lit', is the same as
`.data 200'.
as implements all the standard AMD 29K opcodes. No
additional pseudo-instructions are needed on this family.
For information on the 29K machine instruction set, see Am29000 User's Manual, Advanced Micro Devices, Inc.
as has no additional command-line options for the Hitachi
H8/300 family.
`;' is the line comment character.
`$' can be used instead of a newline to separate statements. Therefore you may not use `$' in symbol names on the H8/300.
You can use predefined symbols of the form `rnh' and `rnl' to refer to the H8/300 registers as sixteen 8-bit general-purpose registers. n is a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid register names.
You can also use the eight predefined symbols `rn' to refer to the H8/300 registers as 16-bit registers (you must use this form for addressing).
On the H8/300H, you can also use the eight predefined symbols `ern' (`er0' ... `er7') to refer to the 32-bit general purpose registers.
The two control registers are called pc (program counter; a
16-bit register, except on the H8/300H where it is 24 bits) and
ccr (condition code register; an 8-bit register). r7 is
used as the stack pointer, and can also be called sp.
as understands the following addressing modes for the H8/300:
rn
@rn
@(d, rn)
@(d:16, rn)
@(d:24, rn)
@rn+
@-rn
@aa@aa:8@aa:16@aa:24aa. (The address size `:24' only makes
sense on the H8/300H.)
#xx
#xx:8
#xx:16
#xx:32
as neither
requires this nor uses it--the data size required is taken from
context.
@@aa@@aa:8as neither requires this nor uses it.
The H8/300 family has no hardware floating point, but the .float
directive generates IEEE floating-point numbers for compatibility
with other development tools.
as has only one machine-dependent directive for the
H8/300:
.h8300h
.int emit 32-bit numbers rather than the usual (16-bit)
for the H8/300 family.
On the H8/300 family (including the H8/300H) `.word' directives generate 16-bit numbers.
For detailed information on the H8/300 machine instruction set, see H8/300 Series Programming Manual (Hitachi ADE--602--025). For information specific to the H8/300H, see H8/300H Series Programming Manual (Hitachi).
as implements all the standard H8/300 opcodes. No additional
pseudo-instructions are needed on this family.
Four H8/300 instructions (add, cmp, mov,
sub) are defined with variants using the suffixes `.b',
`.w', and `.l' to specify the size of a memory operand.
as supports these suffixes, but does not require them;
since one of the operands is always a register, as can
deduce the correct size.
For example, since r0 refers to a 16-bit register,
mov r0,@foo is equivalent to mov.w r0,@foo
If you use the size suffixes, as issues a warning when
the suffix and the register size do not match.
as has no additional command-line options for the Hitachi
H8/500 family.
`!' is the line comment character.
`;' can be used instead of a newline to separate statements.
Since `$' has no special meaning, you may use it in symbol names.
You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', `r6', and `r7' to refer to the H8/500 registers.
The H8/500 also has these control registers:
cp
dp
bp
tp
ep
sr
ccr
All registers are 16 bits long. To represent 32 bit numbers, use two
adjacent registers; for distant memory addresses, use one of the segment
pointers (cp for the program counter; dp for
r0--r3; ep for r4 and r5; and
tp for r6 and r7.
as understands the following addressing modes for the H8/500:
Rn
@Rn
@(d:8, Rn)
@(d:16, Rn)
@-Rn
@Rn+
@aa:8
@aa:16
#xx:8
#xx:16
The H8/500 family has no hardware floating point, but the .float
directive generates IEEE floating-point numbers for compatibility
with other development tools.
as has no machine-dependent directives for the H8/500.
However, on this platform the `.int' and `.word' directives
generate 16-bit numbers.
For detailed information on the H8/500 machine instruction set, see H8/500 Series Programming Manual (Hitachi M21T001).
as implements all the standard H8/500 opcodes. No additional
pseudo-instructions are needed on this family.
As a back end for GNU CC as has been throughly tested and should
work extremely well. We have tested it only minimally on hand written assembly
code and no one has tested it much on the assembly output from the HP
compilers.
The format of the debugging sections has changed since the original
as port (version 1.3X) was released; therefore,
you must rebuild all HPPA objects and libraries with the new
assembler so that you can debug the final executable.
The HPPA as port generates a small subset of the relocations
available in the SOM and ELF object file formats. Additional relocation
support will be added as it becomes necessary.
as has no machine-dependent command-line options for the HPPA.
The assembler syntax closely follows the HPPA instruction set reference manual; assembler directives and general syntax closely follow the HPPA assembly language reference manual, with a few noteworthy differences.
First, a colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.
Some obscure expression parsing problems may affect hand written code which
uses the spop instructions, or code which makes significant
use of the ! line separator.
as is much less forgiving about missing arguments and other
similar oversights than the HP assembler. as notifies you
of missing arguments as syntax errors; this is regarded as a feature, not a
bug.
Finally, as allows you to use an external symbol without
explicitly importing the symbol. Warning: in the future this will be
an error for HPPA targets.
Special characters for HPPA targets include:
`;' is the line comment character.
`!' can be used instead of a newline to separate statements.
Since `$' has no special meaning, you may use it in symbol names.
The HPPA family uses IEEE floating-point numbers.
as for the HPPA supports many additional directives for
compatibility with the native assembler. This section describes them only
briefly. For detailed information on HPPA-specific assembler directives, see
HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001).
as does not support the following assembler directives
described in the HP manual:
.endm .liston .enter .locct .leave .macro .listoff
Beyond those implemented for compatibility, as supports one
additional assembler directive for the HPPA: .param. It conveys
register argument locations for static functions. Its syntax closely follows
the .export directive.
These are the additional directives in as for the HPPA:
.block n
.blockz n
.call
.callinfo [ param=value, ... ] [ flag, ... ]
.code
.copyright "string"
.copyright "string"
.enter
.entry
.exit
.export name [ ,typ ] [ ,param=r ]
0 to 3, and
indicates one of four one-word arguments); `rtnval' (the procedure's
result); or `priv_lev' (privilege level). For arguments or the result,
r specifies how to relocate, and must be one of `no' (not
relocatable), `gr' (argument is in general register), `fr' (in
floating point register), or `fu' (upper half of float register).
For `priv_lev', r is an integer.
.half n
as directive .short.
.import name [ ,typ ]
.export; make a procedure available to call. The arguments
use the same conventions as the first two arguments for .export.
.label name
.leave
.origin lc
.org.
.param name [ ,typ ] [ ,param=r ]
.export, but used for static procedures.
.proc
.procend
label .reg expr
.equ; define label with the absolute expression
expr as its value.
.space secname [ ,params ]
.spnum secnam
.space directive.)
.string "str"
.string "str", for information on escape sequences you can use in
as strings.
Warning! The HPPA version of .string differs from the
usual as definition: it does not write a zero byte
after copying str.
.stringz "str"
.string, but appends a zero byte after copying str to object
file.
.subspa name [ ,params ]
.nsubspa name [ ,params ]
.space, but selects a subsection name within the
current section. You may only specify params when you create a
subsection (in the first instance of .subspa for this name).
If specified, the list params declares attributes of the subsection,
identified by keywords. The keywords recognized are `quad=expr'
("quadrant" for this subsection), `align=expr' (alignment for
beginning of this subsection; a power of two), `access=expr' (value
for "access rights" field), `sort=expr' (sorting order for this
subspace in link), `code_only' (subsection contains only code),
`unloadable' (subsection cannot be loaded into memory), `common'
(subsection is common block), `dup_comm' (initialized data may have
duplicate names), or `zero' (subsection is all zeros, do not write in
object file).
.nsubspa always creates a new subspace with the given name, even
if one with the same name already exists.
.version "str"
For detailed information on the HPPA machine instruction set, see PA-RISC Architecture and Instruction Set Reference Manual (HP 09740-90039).
as에는 현재 80386에 관련된 기계 의존적인 옵션은 없다.
gcc와 as의 출력과 함께 호환성을 유지할 목적으로 AT&T
시스템 V/386 어셈블러 문법을 제공한다. 이것은 인텔 문법과 다소간 차이가
있다. 거의 대부분의 80386을 설명하는 문서들은 인텔 문법만을 사용하기
때문에 여기 서는 이러한 차이점들에 대해서 설명한다. 두 문법에서의
주목할 만한 차이점들은 다음과 같다.
작동자에는 피연산자의 크기를 명시하는 하나의 글자가 꼬리에 붙는다.
`b',`w', `l'은 각각 byte, word, long 피연산자를 사용하고
있음을 명시한다. 만약 어떤 접미어도 명령에 붙지 않는다면
as는 대상 레지스터 피연산자(집합의 마지막 하 나)에 기초해
빠진 꼬리를 붙일 것이다. 그래서 `mov %ax, %bx'는 `movw %ax,
%bx' 와 같게 된다. 또한 `mov $1, %bx'는 `movw $1, %bx'가 될 것이다.
그러나 AT&T 유닉스 어셈블러에서 이렇게 적합하지 않게 꼬리가 빠졌다면
꼬리는 암시적 으로 long 피연산자 크기로 가정된다. (이러한 불일치성에는
컴파일러가 항상 명 백하게 작동자에 꼬리를 명시함으로써 컴파일러의
출력에는 별 영향을 미치지 못 한다.)
조금의 예외가 있긴하다. 부호확장과 zero 확장 명령어들은 그것들을 명시할 두 개의 크기가 필요하다. 이러한 명령어들은 부호/제로 확장을 할 from의 크기와 zero 확장될 to의 크기 하나가 필요하다. 이러한 것을 해결하기 위하여 AT&T 문법에서는 두 개의 작동자 접미어(suffix-꼬리)들을 사용한다. AT&T 문법에 서 부호확장과 제로확장에서의 기본적인 명칭은 `movs...' 와 `movz...'같은 것이 다. (인텔문법에서의 `movsx'와 `movzx'). 작동자 접미어들은 이러한 기본 명칭 에 결합되고, from 접미어가 to 접미어보다 먼저온다. 그래서 인텔 문법의 `movsbl %al, %edx' 은 "move sign extend *from* %al *to* %edx"를 의미한다. 가능한 접미어는 `bl'(from byte to long),`bw'(from byte to word), `wl'(from word to long) 이 된다.
AT&T에서는 `cbtw', `cwtl', `cwtd', `cltd'로 호출된다.
as에서는 이렇게 이름 을 부르는 것을 허용한다.
Far call/jump 명령은 AT&T에서는 `lcall', `ljmp'로 불리우나 인텔에서는 `call far', `jump far'로 명칭된다.
레지스터 피연산자는 항상 `%' 접두어가 붙는다. 80386 레지스터의 구성은 다음과 같다.
작동자의 접두어는 뒤따르는 작동자를 변경하기 위해 사용된다. 그것들은 스트링 명령을 반복한다던지, 섹션 오버리드를 제공한다던지, 버스 록 작동을 수행한다던지, 피연산자와 주소의 크기를 제공하는 데 사용된다. (16-bit 피연산자들은 일반적으로 피연산자 크기 작동자 접두어로 32-bit 피연산 자가 될 수 있는 명령어에서 접두어를 붙임으로서 명시된다.) 작동자 접두어들은 보통 피연산자가 없이 하나의 행 명령으로 주어지고 반드시 바로 그것들이 의존하는 명령어들이 앞서야 한다. 예를 들자면 `scas'(scan string) 명령은 다음과 같이 반복된다:
repne
scas
여기에 작동자 접두어들의 목록이 있다.
인텔문법에서 메모리를 간접적으로 참조하는 형식은 다음과 같다.
section:[base + index*scale + disp]
이것은 다음과 같은 AT&T 방식으로 참조된다.
section:disp(base, index, scale)
base와 index는 32비트 베이스와 인덱스 레지스터이고,
disp와 함께 선택사항이다. scale 은 피연산자의 주소를
계산하기 위하여 index에 곱해지는 1, 2, 4, 8과 같은 것이다.
scale이 명시되지 않으면 그것은 1로 취급 된다. section 에는
메모리 피연산자를 위한 섹션 레지스터를 명시한다. 이것은 아마도 디폴트
섹션 레지스터로 채워질 것이다. (디폴트 섹션 레지스터는 80386 메뉴얼을
참고하라) 물론 이것도 선택사항이다. 이 섹션은 AT&T 문법상에서는
반드시 `%'가 앞에 나오는 형태이어야 한다. 만일 디폴트 섹션
레지스터와 같이 동시에 해석할 소지가 있는 것으로 섹션을 명시한다면,
as는 주어진 명령을 어셈블할 때에 그 부분을 뒤덥어 버리는
어떠한 접두어 섹션 레지스터도 출력하지 않을 것이다. 그래서, 섹션
쓰기는 주어진 메모리를 참조하는 데 있어서 어떠한 섹션레지스터가 사용될
것인지를 강조하여 명시할 수 있다.
여기에 인텔과 AT&T 스타일의 메모리 참조를 하는 몇몇 예를 싣는다.
절대적인(PC와는 달리) call과 jump 피연산자들은 반드시 `*'가 앞에 와야 한다. `*'가 명시되지 않으면, as는 항상 PC와 같은 형태의 jump/call 라벨을 어드레싱한다.
메모리 피연산자를 가지는 어떤 명령어들도 반드시 그것의 크기(byte, word, long)를 작동자의 접미어(`b', `w', `l')로 명시해야 한다.
점프 명령어들은 가능한 최소의 이동이 일어나도록 최적화된다. 이것은 점프 대상이 충분히 가까울 때는 언제나 1바이트(8비트) 위치이동 점프를 사용함으로써 가능하다. 1바이트 위치이동이 불충분 하다면 long(32비트) 위치이동 점프가 사용된다. 우리는 word(16비트) 위치이동 점프는 제공하 지 않는다(`addr16' 작동자 접두어와 같은 점프 명령이 선행하는 것과 같 은..). 80386 이 `%eip'를 16 비트로 마스킹하기를 주장한 이후에나 워드 위치이동 점프가 추가되었다.
`jcxz', `jecxz', `loop', `loopz', `loope', `loopnz', `loopne' 명령들은 단지 바이트 위치이동에서만 사용된다. 그래서 이와 비슷한 다른 명령어들을 사용한다면 ('gcc'는 이것들을 사용하지 못한다) 에러메세지와 함께 틀린 코드 부분을 출력 할 것이다. AT&T 80386 어셈블러에서는 이러한 문제점 을 다음과 같이 해결한다. `jcxz foo'를.
jcxz cx_zero
jmp cx_nonzero
cx_zero: jmp foo
cx_nonzero:
BCD 관련되는 것만 제외하고는 모든 80387 부동소수점 타입이 제공된다. (BCD를 제공하는 것도 그다지 어렵지 않을 것이다). 이러한 데이터 타입 은 16, 32, 64 비트 정수형과, single (32비트), double (64비트), 확장 (80비트) 정밀도의 부동 소수점이다. 제공되는 각각의 타입은 작동자 접미어 가 따라 붙으며, 그것과 결합한 생성자를 가진다. 작동자의 접미어는 피연산자 의 데이터 타입을 명시한다. 생성자는 이러한 데이터 타입을 메모리에 만든다.
레지스터에서 레지스터로 작동하는 것에는 작동자 뒤에 붙이는 접미어가 필요치 않다. 그래서 `fst %st, %st(1)'은 `fstl %st, %st(1)'과 같다.
80387 이 자동적으로 80386의 `fwait'명령과 동시에 발생시킬 필요성은
거의 필요치 않다 (이 경우는 80286/80287과 8086/8087 의 짝들에는 해당되지
않는다.) 그러므로 as는 `fn...' 명령중의 하나에
의해 `fwait'가 암시적으로 선택되었을 때에는 `fwait'명령을
억제한다. 예를 들면, `fsave'와 `fnsave'는 똑같이 취급 된다.
일반적으로, 모든 `fn...' 명령은 `f...'명령과 동등하다.
만일 `fwait'를 쓰 고자 한다면 그것은 정확히 코드속에 포함하여야
한다.
While GAS normally writes only "pure" 32-bit i386 code, it has limited support for writing code to run in real mode or in 16-bit protected mode code segments. To do this, insert a `.code16' directive before the assembly language instructions to be run in 16-bit mode. You can switch GAS back to writing normal 32-bit code with the `.code32' directive.
GAS understands exactly the same assembly language syntax in 16-bit mode as in 32-bit mode. The function of any given instruction is exactly the same regardless of mode, as long as the resulting object code is executed in the mode for which GAS wrote it. So, for example, the `ret' mnemonic produces a 32-bit return instruction regardless of whether it is to be run in 16-bit or 32-bit mode. (If GAS is in 16-bit mode, it will add an operand size prefix to the instruction to force it to be a 32-bit return.)
This means, for one thing, that you can use GNU CC to write code to be run in real mode or 16-bit protected mode. Just insert the statement `asm(".code16");' at the beginning of your C source file, and while GNU CC will still be generating 32-bit code, GAS will automatically add all the necessary size prefixes to make that code run in 16-bit mode. Of course, since GNU CC only writes small-model code (it doesn't know how to attach segment selectors to pointers like native x86 compilers do), any 16-bit code you write with GNU CC will essentially be limited to a 64K address space. Also, there will be a code size and performance penalty due to all the extra address and operand size prefixes GAS has to add to the instructions.
Note that placing GAS in 16-bit mode does not mean that the resulting code will necessarily run on a 16-bit pre-80386 processor. To write code that runs on such a processor, you would have to refrain from using any 32-bit constructs which require GAS to output address or operand size prefixes. At the moment this would be rather difficult, because GAS currently supports only 32-bit addressing modes: when writing 16-bit code, it always outputs address size prefixes for any instruction that uses a non-register addressing mode. So you can write code that runs on 16-bit processors, but only if that code never references memory.
여기서는 `mul'과 `imul' 명령과 관련된 언급할 만한 몇가지
트릭을 설명하겠다. 16, 32, 64 비트로 결과물이 확장되는 곱셈은 단지
하나의 피연산자에 출력될 것이다. 그러므로, `imul %ebx, %eax'는
곱셈의 결과가 원하는 데로 확장되지 않을 것이 다; 확장을 기대하는 곱셈은
`%edx' 레지스터를 덮어 쓸 것이며, gcc가 출력을
하고자 하는 데 혼란을 줄 것이다. `%edx:%eax'에 64비트 결과물을
얻을려면 `imul %ebx'를 사용하라.
우리는 `imul'과 관련된 2개의 피연산자 형을 추가하였다. 그것은 첫 번째 피연산 자가 즉각적인 값을 갖는 (역자주: 상수형태와 비슷한) 표현이고 두 번째 피연산 자는 레지스터이다. `%eax'에 69를 곱하는 것을 예로 들면, `imul $69, %eax, %eax'보다는 `imul $69, %eax'이 될 수 있을 것이다.
-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
as generates code
for any instruction or feature that is supported by some version of the
960 (even if this means mixing architectures!). In principle,
as attempts to deduce the minimal sufficient processor type if
none is specified; depending on the object code format, the processor type may
be recorded in the object file. If it is critical that the as
output match a specific architecture, specify that architecture explicitly.
-b
call increment routine
.word 0 # pre-counter
Label: BR
call increment routine
.word 0 # post-counter
The counter following a branch records the number of times that branch
was not taken; the differenc between the two counters is the
number of times the branch was taken.
A table of every such Label is also generated, so that the
external postprocessor gbr960 (supplied by Intel) can locate all
the counters. This table is always labelled `__BRANCH_TABLE__';
this is a local symbol to permit collecting statistics for many separate
object files. The table is word aligned, and begins with a two-word
header. The first word, initialized to 0, is used in maintaining linked
lists of branch tables. The second word is a count of the number of
entries in the table, which follow immediately: each is a word, pointing
to one of the labels illustrated above.
The first word of the header is used to locate multiple branch tables,
since each object file may contain one. Normally the links are
maintained with a call to an initialization routine, placed at the
beginning of each function in the file. The GNU C compiler
generates these calls automatically when you give it a `-b' option.
For further details, see the documentation of `gbr960'.
-no-relax
as should generate errors instead, if the target displacement
is larger than 13 bits.
This option does not affect the Compare-and-Jump instructions; the code
emitted for them is always adjusted when necessary (depending on
displacement size), regardless of whether you use `-no-relax'.
as generates IEEE floating-point numbers for the directives
`.float', `.double', `.extended', and `.single'.
.bss symbol, length, align
.lcomm symbol , length.
.extended flonums
.extended expects zero or more flonums, separated by commas; for
each flonum, `.extended' emits an IEEE extended-format (80-bit)
floating-point number.
.leafproc call-lab, bal-lab
callj instruction to enable faster calls of leaf
procedures. If a procedure is known to call no other procedures, you
may define an entry point that skips procedure prolog code (and that does
not depend on system-supplied saved context), and declare it as the
bal-lab using `.leafproc'. If the procedure also has an
entry point that goes through the normal prolog, you can specify that
entry point as call-lab.
A `.leafproc' declaration is meant for use in conjunction with the
optimized call instruction `callj'; the directive records the data
needed later to choose between converting the `callj' into a
bal or a call.
call-lab is optional; if only one argument is present, or if the
two arguments are identical, the single argument is assumed to be the
bal entry point.
.sysproc name, index
All Intel 960 machine instructions are supported; see section i960 Command-line Options for a discussion of selecting the instruction subset for a particular 960 architecture.
Some opcodes are processed beyond simply emitting a single corresponding instruction: `callj', and Compare-and-Branch or Compare-and-Jump instructions with target displacements larger than 13 bits.
callj
You can write callj to have the assembler or the linker determine
the most appropriate form of subroutine call: `call',
`bal', or `calls'. If the assembly source contains
enough information--a `.leafproc' or `.sysproc' directive
defining the operand--then as translates the
callj; if not, it simply emits the callj, leaving it
for the linker to resolve.
The 960 architectures provide combined Compare-and-Branch instructions that permit you to store the branch target in the lower 13 bits of the instruction word itself. However, if you specify a branch target far enough away that its address won't fit in 13 bits, the assembler can either issue an error, or convert your Compare-and-Branch instruction into separate instructions to do the compare and the branch.
Whether as gives an error or expands the instruction depends
on two choices you can make: whether you use the `-no-relax' option,
and whether you use a "Compare and Branch" instruction or a "Compare
and Jump" instruction. The "Jump" instructions are always
expanded if necessary; the "Branch" instructions are expanded when
necessary unless you specify -no-relax---in which case
as gives an error instead.
These are the Compare-and-Branch instructions, their "Jump" variants, and the instruction pairs they may expand into:
as의 Motorola 680x0 버전에는 기계 의존적인 옵션이 몇개
있다.
정의되지 않은 심볼에 대해 참조하는 크기를 줄이려면 `-l' 옵션을
사용한다. `-l' 옵션을 사용하지 않으면, 정의되지 않은 심볼에 대한
참조는 long을 완전히 채울만큼 클 것이다. (as는 이
심볼이 어디서 끝날지 모르기 때문에, as는 훗날의 링커를
위해서 공간을 할당해 두는 수밖에 없다. as는 이 심볼이
얼마나 멀리 있는지 모르기 때문에, 가능한한 많은 공간을 확보한다.) 이
옵션을 사용하면, 이러한 참조는 한개의 word 크기(16 비트)가 된다. 이
기능은 목적 파일을 가능한한 작게 하고 싶으면서 관련된 심볼이 언제나
17비트 이내의 거리에 있다는 것을 안다면 유용하게 쓰일 수 있다.
For some configurations, especially those where the compiler normally does not prepend an underscore to the names of user variables, the assembler requires a `%' before any use of a register name. This is intended to let the assembler distinguish between C variables and functions named `a0' through `a7', and so on. The `%' is always accepted, but is not required for certain configurations, notably `sun3'. The `--register-prefix-optional' option may be used to permit omitting the `%' even for configurations for which it is normally required. If this is done, it will generally be impossible to refer to C variables and functions with the same names as register names.
Normally the character `|' is treated as a comment character, which means that it can not be used in expressions. The `--bitwise-or' option turns `|' into a normal character. In this mode, you must either use C style comments, or start comments with a `#' character at the beginning of a line.
as can assemble code for several different members of the
Motorola 680x0 family. The default depends upon how as
was configured when it was built; normally, the default is to assemble
code for the 68020 microprocessor. The following options may be used to
change the default. These options control which instructions and
addressing modes are permitted. The members of the 680x0 family are
very similar. For detailed information about the differences, see the
Motorola manuals.
This syntax for the Motorola 680x0 was developed at MIT.
The 680x0 version of as uses instructions names and
syntax compatible with the Sun assembler. Intervening periods are
ignored; for example, `movl' is equivalent to `mov.l'.
In the following table apc stands for any of the address registers (`%a0' through `%a7'), the program counter (`%pc'), the zero-address relative to the program counter (`%zpc'), a suppressed address register (`%za0' through `%za7'), or it may be omitted entirely. The use of size means one of `w' or `l', and it may be omitted, along with the leading colon, unless a scale is also specified. The use of scale means one of `1', `2', `4', or `8', and it may always be omitted along with the leading colon.
The following addressing modes are understood:
%a6
is also known as `%fp', the Frame Pointer.
The standard Motorola syntax for this chip differs from the syntax
already discussed (see section Syntax). as can
accept Motorola syntax for operands, even if MIT syntax is used for
other operands in the same instruction. The two kinds of syntax are
fully compatible.
In the following table apc stands for any of the address registers (`%a0' through `%a7'), the program counter (`%pc'), the zero-address relative to the program counter (`%zpc'), or a suppressed address register (`%za0' through `%za7'). The use of size means one of `w' or `l', and it may always be omitted along with the leading dot. The use of scale means one of `1', `2', `4', or `8', and it may always be omitted along with the leading asterisk.
The following additional addressing modes are understood:
%a6
is also known as `%fp', the Frame Pointer.
Packed decimal (P) format floating literals are not supported. Feel free to add the code!
The floating point formats generated by directives are these.
.float
Single precision floating point constants.
.double
Double precision floating point constants.
.extend
.ldouble
Extended precision (long double) floating point constants.
In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives.
.data1
.data 1 directive.
.data2
.data 2 directive.
.even
.align directive; it
aligns the output to an even byte boundary.
.skip
.space directive.
Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by substituting `j' for `b' at the start of a Motorola mnemonic.
The following table summarizes the pseudo-operations. A * flags
cases that are more fully described after the table:
Displacement
+-------------------------------------------------
| 68020 68000/10
Pseudo-Op |BYTE WORD LONG LONG non-PC relative
+-------------------------------------------------
jbsr |bsrs bsr bsrl jsr jsr
jra |bras bra bral jmp jmp
* jXX |bXXs bXX bXXl bNXs;jmpl bNXs;jmp
* dbXX |dbXX dbXX dbXX; bra; jmpl
* fjXX |fbXXw fbXXw fbXXl fbNXw;jmp
XX: condition
NX: negative of condition XX
*---see full description below
jbsr
jra
jXX
jhi jls jcc jcs jne jeq jvc jvs jpl jmi jge jlt jgt jleFor the cases of non-PC relative displacements and long displacements on the 68000 or 68010,
as issues a longer code fragment in terms of
NX, the opposite condition to XX. For example, for the
non-PC relative case:
jXX foo
gives
bNXs oof
jmp foo
oof:
dbXX
dbhi dbls dbcc dbcs dbne dbeq dbvc dbvs dbpl dbmi dbge dblt dbgt dble dbf dbra dbtOther than for word and byte displacements, when the source reads `dbXX foo',
as emits
dbXX oo1
bra oo2
oo1:jmpl foo
oo2:
fjXX
fjne fjeq fjge fjlt fjgt fjle fjf fjt fjgl fjgle fjnge fjngl fjngle fjngt fjnle fjnlt fjoge fjogl fjogt fjole fjolt fjor fjseq fjsf fjsne fjst fjueq fjuge fjugt fjule fjult fjunFor branch targets that are not PC relative,
as emits
fbNX oof
jmp foo
oof:
when it encounters `fjXX foo'.
The immediate character is `#' for Sun compatibility. The line-comment character is `|' (unless the `--bitwise-or' option is used). If a `#' appears at the beginning of a line, it is treated as a comment unless it looks like `# line file', in which case it is treated normally.
GNU as for MIPS architectures supports the MIPS
R2000, R3000, R4000 and R6000 processors. For information
about the MIPS instruction set, see MIPS RISC Architecture, by Kane
and Heindrich (Prentice-Hall). For an overview of MIPS assembly
conventions, see "Appendix D: Assembly Language Programming" in the same
work.
The MIPS configurations of GNU as support these
special options:
-G num
gp register. It is only accepted for targets
that use ECOFF format. The default value is 8.
-EB
-EL
as can select big-endian or
little-endian output at run time (unlike the other GNU development
tools, which must be configured for one or the other). Use `-EB'
to select big-endian output, and `-EL' for little-endian.
-mips1
-mips2
-mips3
-m4650
-no-m4650
-m4010
-no-m4010
-mcpu=CPU
gcc.
-nocpp
as, there is no need for `-nocpp', because the
GNU assembler itself never runs the C preprocessor.
--trap
--no-break
as automatically macro expands certain division and
multiplication instructions to check for overflow and division by zero. This
option causes as to generate code to take a trap exception
rather than a break exception when an error is detected. The trap instructions
are only supported at Instruction Set Architecture level 2 and higher.
--break
--no-trap
Assembling for a MIPS ECOFF target supports some additional sections
besides the usual .text, .data and .bss. The
additional sections are .rdata, used for read-only data,
.sdata, used for small data, and .sbss, used for small
common objects.
When assembling for ECOFF, the assembler uses the $gp ($28)
register to form the address of a "small object". Any object in the
.sdata or .sbss sections is considered "small" in this sense.
For external objects, or for objects in the .bss section, you can use
the gcc `-G' option to control the size of objects addressed via
$gp; the default value is 8, meaning that a reference to any object
eight bytes or smaller uses $gp. Passing `-G 0' to
as prevents it from using the $gp register on the basis
of object size (but the assembler uses $gp for objects in .sdata
or sbss in any case). The size of an object in the .bss section
is set by the .comm or .lcomm directive that defines it. The
size of an external object may be set with the .extern directive. For
example, `.extern sym,4' declares that the object at sym is 4 bytes
in length, whie leaving sym otherwise undefined.
Using small ECOFF objects requires linker support, and assumes that the
$gp register is correctly initialized (normally done automatically by
the startup code). MIPS ECOFF assembly code must not modify the
$gp register.
MIPS ECOFF as supports several directives used for
generating debugging information which are not support by traditional MIPS
assemblers. These are .def, .endef, .dim, .file,
.scl, .size, .tag, .type, .val,
.stabd, .stabn, and .stabs. The debugging information
generated by the three .stab directives can only be read by GDB,
not by traditional MIPS debuggers (this enhancement is required to fully
support C++ debugging). These directives are primarily used by compilers, not
assembly language programmers!
GNU as supports an additional directive to change the
MIPS Instruction Set Architecture level on the fly: .set
mipsn. n should be a number from 0 to 3. A value from 1 to 3
makes the assembler accept instructions for the corresponding ISA level,
from that point on in the assembly. .set mipsn affects not only
which instructions are permitted, but also how certain macros are expanded.
.set mips0 restores the ISA level to its original level: either the
level you selected with command line options, or the default for your
configuration. You can use this feature to permit specific R4000
instructions while assembling in 32 bit mode. Use this directive with care!
Traditional MIPS assemblers do not support this directive.
as has no additional command-line options for the Hitachi
SH family.
`!' is the line comment character.
You can use `;' instead of a newline to separate statements.
Since `$' has no special meaning, you may use it in symbol names.
You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', `r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to refer to the SH registers.
The SH also has these control registers:
pr
pc
mach
macl
sr
gbr
vbr
as understands the following addressing modes for the SH.
Rn in the following refers to any of the numbered
registers, but not the control registers.
Rn
@Rn
@-Rn
@Rn+
@(disp, Rn)
@(R0, Rn)
@(disp, GBR)
GBR offset
@(R0, GBR)
addr
@(disp, PC)
as implementation allows you to use the simpler form
addr anywhere a PC relative address is called for; the alternate
form is supported for compatibility with other assemblers.
#imm
The SH family has no hardware floating point, but the .float
directive generates IEEE floating-point numbers for compatibility
with other development tools.
as has no machine-dependent directives for the SH.
For detailed information on the SH machine instruction set, see SH-Microcomputer User's Manual (Hitachi Micro Systems, Inc.).
as implements all the standard SH opcodes. No additional
pseudo-instructions are needed on this family. Note, however, that
because as supports a simpler form of PC-relative
addressing, you may simply write (for example)
mov.l bar,r0
where other assemblers might require an explicit displacement to
bar from the program counter:
mov.l @(disp, PC)
The SPARC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level. There are exceptions to this however. For details on what instructions each variant supports, please see the chip's architecture reference manual.
By default, as assumes the core instruction set (SPARC
v6), but "bumps" the architecture level as needed: it switches to
successively higher architectures as it encounters instructions that
only exist in the higher levels.
If not configured for SPARC v9 (sparc64-*-*) GAS will not bump
passed sparclite by default, an option must be passed to enable the
v9 instructions.
GAS treats sparclite as being compatible with v8, unless an architecture is explicitly requested. SPARC v9 is always incompatible with sparclite.
-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite | -Av9 | -Av9a
as reports a fatal error if it encounters an instruction
or feature requiring a higher level.
-xarch=v8plus | -xarch=v8plusa
-bump
The Sparc uses IEEE floating-point numbers.
The Sparc version of as supports the following additional
machine directives:
.align
.common
"bss". This behaves somewhat like .comm, but the
syntax is different.
.half
.short.
.proc
.reserve
"bss". This behaves somewhat like .lcomm, but the
syntax is different.
.seg
"text", "data", or
"data1". It behaves like .text, .data, or
.data 1.
.skip
.space directive.
.word
.word directive produces 32 bit values,
instead of the 16 bit values it produces on many other machines.
.xword
.xword directive produces
64 bit values.
The Z8000 as supports both members of the Z8000 family: the unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit addresses.
When the assembler is in unsegmented mode (specified with the
unsegm directive), an address takes up one word (16 bit)
sized register. When the assembler is in segmented mode (specified with
the segm directive), a 24-bit address takes up a long (32 bit)
register. See section Assembler Directives for the Z8000,
for a list of other Z8000 specific assembler directives.
as has no additional command-line options for the Zilog
Z8000 family.
`!' is the line comment character.
You can use `;' instead of a newline to separate statements.
The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer to different sized groups of registers by register number, with the prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for 64 bit registers. You can also refer to the contents of the first eight (of the sixteen 16 bit registers) by bytes. They are named `rnh' and `rnl'.
byte registers r0l r0h r1h r1l r2h r2l r3h r3l r4h r4l r5h r5l r6h r6l r7h r7l word registers r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 long word registers rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 quad word registers rq0 rq4 rq8 rq12
as understands the following addressing modes for the Z8000:
rn
@rn
addr
address(rn)
rn(#imm)
rn(rm)
#xx
The Z8000 port of as includes these additional assembler directives, for compatibility with other Z8000 assemblers. As shown, these do not begin with `.' (unlike the ordinary as directives).
segm
unsegm
name
.file
global
.global
wval
.word
lval
.long
bval
.byte
sval
sval expects one string literal, delimited by
single quotes. It assembles each byte of the string into consecutive
addresses. You can use the escape sequence `%xx' (where
xx represents a two-digit hexadecimal number) to represent the
character whose ASCII value is xx. Use this feature to
describe single quote and other characters that may not appear in string
literals as themselves. For example, the C statement `char *a =
"he said \"it's 50% off\"";' is represented in Z8000 assembly language
(shown with the assembler output in hex at the left) as
@begingroup
@let@nonarrowing=@comment
68652073 sval 'he said %22it%27s 50%25 off%22%00' 61696420 22697427 73203530 25206F66 662200@endgroup
rsect
.section
block
.space
even
.align; aligns output to even byte boundary.
For detailed information on the Z8000 machine instruction set, see Z8000 Technical Manual.
The Vax version of as accepts any of the following options,
gives a warning message that the option was ignored and proceeds.
These options are for compatibility with scripts designed for other
people's assemblers.
-D (Debug)-S (Symbol Table)-T (Token Trace)-d (Displacement size for JUMPs)-V (Virtualize Interpass Temporary File)as always does this, so this
option is redundant.
-J (JUMPify Longer Branches)-t (Temporary File Directory)as does not use a temporary disk file, this
option makes no difference. `-t' needs exactly one
filename.
The Vax version of the assembler accepts two options when
compiled for VMS. They are `-h', and `-+'. The
`-h' option prevents as from modifying the
symbol-table entries for symbols that contain lowercase
characters (I think). The `-+' option causes as to
print warning messages if the FILENAME part of the object file,
or any symbol name is larger than 31 characters. The `-+'
option also inserts some code following the `_main'
symbol so that the object file is compatible with Vax-11
"C".
Conversion of flonums to floating point is correct, and compatible with previous assemblers. Rounding is towards zero if the remainder is exactly half the least significant bit.
D, F, G and H floating point formats
are understood.
Immediate floating literals (e.g. `S`$6.9') are rendered correctly. Again, rounding is towards zero in the boundary case.
The .float directive produces f format numbers.
The .double directive produces d format numbers.
The Vax version of the assembler supports four directives for generating Vax floating point constants. They are described in the table below.
.dfloat
d format 64-bit floating point constants.
.ffloat
f format 32-bit floating point constants.
.gfloat
g format 64-bit floating point constants.
.hfloat
h format 128-bit floating point constants.
All DEC mnemonics are supported. Beware that case...
instructions have exactly 3 operands. The dispatch table that
follows the case... instruction should be made with
.word statements. This is compatible with all unix
assemblers we know of.
Certain pseudo opcodes are permitted. They are for branch instructions. They expand to the shortest branch instruction that reaches the target. Generally these mnemonics are made by substituting `j' for `b' at the start of a DEC mnemonic. This feature is included both for compatibility and to help compilers. If you do not need this feature, avoid these opcodes. Here are the mnemonics, and the code they can expand into.
jbsb
jbr
jr
jCOND
neq, nequ, eql, eqlu, gtr,
geq, lss, gtru, lequ, vc, vs,
gequ, cc, lssu, cs.
COND may also be one of the bit tests
bs, bc, bss, bcs, bsc, bcc,
bssi, bcci, lbs, lbc.
NOTCOND is the opposite condition to COND.
jacbX
b d f g h l w.
OPCODE ..., foo ; brb bar ; foo: jmp ... ; bar:
jaobYYY
lss leq.
jsobZZZ
geq gtr.
OPCODE ..., foo ; brb bar ; foo: brw destination ; bar:
OPCODE ..., foo ; brb bar ; foo: jmp destination ; bar:
aobleq
aoblss
sobgeq
sobgtr
OPCODE ..., foo ; brb bar ; foo: brw destination ; bar:
OPCODE ..., foo ; brb bar ; foo: jmp destination ; bar:
The immediate character is `$' for Unix compatibility, not `#' as DEC writes it.
The indirect character is `*' for Unix compatibility, not `@' as DEC writes it.
The displacement sizing character is ``' (an accent grave) for
Unix compatibility, not `^' as DEC writes it. The letter
preceding ``' may have either case. `G' is not
understood, but all other letters (b i l s w) are understood.
Register names understood are r0 r1 r2 ... r15 ap fp sp
pc. Upper and lower case letters are equivalent.
For instance
tstb *w`$4(r5)
Any expression is permitted in an operand. Operands are comma separated.
Vax bit fields can not be assembled with as. Someone
can add the required code if they really need it.
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